Buch

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Übersicht

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Verlag	:	Springer International Publishing
Buchreihe	:	Undergraduate Topics in Computer Science
Sprache	:	Englisch
Erschienen	:	08. 12. 2022
Seiten	:	380
Einband	:	Kartoniert
Höhe	:	235 mm
Breite	:	155 mm
ISBN	:	9783031180224
Sprache	:	Englisch
Illustrationen	:	XV, 380 p.

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Autorinformation

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Bernard Goossens is Professor in the Faculty of Sciences at the Université de Perpignan, France.  He is the author of the French-language book from Springer, Architecture et microarchitecture des processeurs, 2002.

Inhaltsverzeichnis

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Part I. Single core processors.- 1. Getting Ready.- 2.  Building a RISC-V Processor.- 3. Building a Pipelined RISC-V Processor.- 4. Building a RISC-V Processor with a Multi-cycle Pipeline.- 5.  Building a RISC-V Processor with a Multiple Hart Pipeline.- Part II. Multiple core processors.- 6. Connecting IPs.- 7. A Multi-core RISC-V Processor.- 8. A Multi-core RISC-V Processor with Multi-hart Cores.

Deine Buchhandlung

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